Business & funding · first seen 5h ago, updated 5h ago
Cadence Expands TSMC Partnership for AI and HPC Chip Design
Expanded partnership spans TSMC A14 certification, silicon-proven IP on TSMC N3P/N2P, wafer-scale 3D-IC for hundreds of chiplets, and agentic AI flows SAN JOSE, Calif., Sept. 24, 2026 — Cadence has announced an expanded partnership with TSM…
Summary from AIwire (HPCwire).
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AIwire (HPCwire)Cadence Expands TSMC Partnership for AI and HPC Chip Design